Several trends exist presently in the semiconductor and electronics industry. Devices are continually getting smaller, faster and requiring less power. A reason for these trends is that more personal devices are being fabricated which are relatively small and portable, thereby relying on a battery as its primary supply source. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and speed. In light of all these trends, there is an ever increasing demand in the industry for smaller and faster transistors used to provide the core functionality of the integrated circuits used in these devices.
Accordingly, in the semiconductor industry there is a continuing trend toward manufacturing integrated circuits (ICs) with higher densities. To achieve high densities, there has been and continues to be efforts toward scaling down dimensions (e.g., at submicron levels) on semiconductor wafers, which are generally produced from bulk silicon. In order to accomplish such high densities, smaller feature sizes, smaller separations between features and more precise feature shapes are required in integrated circuits (ICs) fabricated on small rectangular portions of the wafer, commonly known as dies. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, as well as the surface geometry of various other features (e.g., corners and edges). The scaling-down of integrated circuit dimensions can facilitate faster circuit performance and/or switching speeds, and can lead to higher effective yield in IC fabrication by providing more circuits on a die and/or more die per semiconductor wafer.
The process of manufacturing integrated circuits typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit can be formed on a single wafer. This process can create electrically active regions in and on the semiconductor wafer surface. In MOS transistors, for example, a gate structure is created, which can be energized to establish an electric field within a semiconductor channel, by which current is enabled to flow between a source region and a drain region within the transistor. The source and drain regions facilitate this conductance by virtue of containing a majority of positively doped (p) or negatively doped (n) materials.
As device sizes continue to shrink, however, the channel lengths continue to be scaled downward, and short channel effects can become significant. For example, hot carrier effects can be experienced in short channel devices. More particularly, during saturation operation of a MOS transistor, for example, electrons can gain kinetic energy and become “hot”. Some of these hot electrons traveling to the drain can be injected into a thin gate dielectric proximate the drain junction. The injected hot carriers, in turn, often lead to undesired degradation of the MOS device operating parameters, such as a shift in threshold voltage, changed transconductance, changed drive current/drain current exchange, device instability, etc.
Similarly, unwanted source/drain leakage conduction or punchthrough current can occur as channel lengths shorten. Punchthrough current may be seen as a parasitic current path existing between the drain and source, which the gate has difficulty in controlling since the current path is located deep in the bulk (substrate) far away from the gate. The actual amount of punchthrough current depends mainly upon the potential distribution under the channel and on the source/drain junction depths. As the effective channel length gets shorter, the source/drain depletion regions get closer together. Punchthrough generally occurs when the effective channel length is decreased to roughly the sum of two junction depletion widths.
In addition, as device densities and operational speeds continue to increase, reduction of the delay times in the MOS devices used in integrated circuits is desired. These delays are related to the on-state resistance as well as the junction capacitances of these MOS devices. Working with smaller and more densely packed devices, however, requires a greater precision in fabrication, which can provide opportunities for errors to occur. For example, dopant may be unintentionally placed in unwanted areas and may increase junction capacitance and cause body leakage, resulting in reduced switching speeds and higher source to drain resistance (Rsd). Imprecisely placed dopants may also migrate into a channel region, for example, and shorten the channel length adding to possible subsurface leakage current paths.
Accordingly, improved techniques for fabricating densely packed semiconductor devices would be desirable. More particularly, it would be desirable to fabricate semiconductor devices in a manner that mitigates short channel effects. Similarly, it would also be desirable to fashion semiconductor devices such that junction capacitances are reduced and switching speeds are thereby enhanced.